Commit 4120e56f authored by Mathieu Maret's avatar Mathieu Maret

Correct outb usage

parent f18249fa
......@@ -17,29 +17,29 @@
void initPic(void)
{
/* Send CMD: Init + sequence in 4 DATA */
outb(ICW1_INIT + ICW1_ICW4, PIC_MASTER_CMD);
outb(ICW1_INIT + ICW1_ICW4, PIC_SLAVE_CMD);
outb(PIC_MASTER_CMD, ICW1_INIT + ICW1_ICW4);
outb(PIC_SLAVE_CMD, ICW1_INIT + ICW1_ICW4);
/* Send ICW2: ctrl base address. Remap IRQ from interupt range 0x0-0xF to 0x20-0x2F as
* intel
* reserve interupt 0x0-0x1F in protected mode (e.g. 0-7 are CPU exception) */
outb(IRQ_INTERRUPT_BASE_ADDRESS, PIC_MASTER_DATA);
outb(IRQ_INTERRUPT_BASE_ADDRESS + 8, PIC_SLAVE_DATA);
outb(PIC_MASTER_DATA, IRQ_INTERRUPT_BASE_ADDRESS);
outb(PIC_SLAVE_DATA, IRQ_INTERRUPT_BASE_ADDRESS +8);
/* Send ICW3 master: mask where slaves are connected */
outb(0x4, PIC_MASTER_DATA);
outb(PIC_MASTER_DATA, 0x4);
/* Send ICW3 slave: index where the slave is connected on master */
outb(0x2, PIC_SLAVE_DATA);
outb(PIC_SLAVE_DATA, 0x2);
/* Send ICW4: 8086 mode, fully nested, not buffered, no implicit EOI */
outb(ICW4_8086, PIC_MASTER_DATA);
outb(ICW4_8086, PIC_SLAVE_DATA);
outb(PIC_MASTER_DATA, ICW4_8086);
outb(PIC_SLAVE_DATA, ICW4_8086);
/* Send OCW1:
* Closing all IRQs : waiting for a correct handler The only IRQ
* enabled is the cascade (that's why we use 0xFB for the master) */
outb(0xFB, PIC_MASTER_DATA);
outb(0xFF, PIC_SLAVE_DATA);
outb(PIC_MASTER_DATA, 0xFB);
outb(PIC_SLAVE_DATA, 0xFF);
}
void enableIrq(int irq)
......
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